Note: The following provides a suggested course description, objectives, and an outline. These may be modified pending discussion with the Faculty Chairs, proposing faculty, and other curriculum reviewers.

Course Description: This course will provide an overview of issues related to the testing and reliability of VLSI circuits. A wide range of VLSI testability analysis and design methods will be covered to give and prepare the students for the modern industrial and academic environments.

Course Objectives: To enable students to understand how to test VLSI circuits that they design or use.

Course Outline by Topical Areas:

• Logic Simulation (Compiled and Event-Driven Simulation).
• Fault Modeling (Defects vs. Faults, Redundancy, Stuck-at, Bridging, Delay).
• Fault Simulation (Serial, Deductive, Concurrent).
• Combinational Test Generation (Path Sensitization, D-alg, PODEM, FAN).
• Sequential Test Generation (Time-Frame Expansion, Initializability, Reachability).
• Design for Testability (Test Points, Full and Partial Scan).
• Built-In Self Test (Pseudo-Random Pattern Generation, BIST Architectures).
• Embedded care test and FPGh test.